U.S. Pat. No. 4,430,721, which was issued Feb. 7, 1984 in the name of Acampora, describes a linear phase digital filter processor in which digital data is delayed in a shift register, then symmetrically tapped around a center tap, and added in pairs from the outside taps inward to build up "powers of two" filter functions. Each tap is weighted by bit-shifting the delayed data before it is added. U.S. Pat. No. 4,524,423, which was issued Jun. 18, 1985 also in the name of Acampora, shows a similar filter configuration where, because the filter coefficient values are symmetrical around the center tap, the data from symmetrical taps are first added and then the sum is bit-shifted to achieve "powers of two" functions. U.S. Pat. No. 4,615,026, which was issued Sep. 30, 1986 in the name of Schiff, shows a shift and add weighting circuit for a digital filter in which the arithmetic bit-shifting circuits are responsive to control signals that determine the magnitude of each shift.
The Acampora and Schiff references teach specific architectures for a one-dimensional digital filter. There is a need, particularly in ASIC (Application Specific Integrated Circuit) implementations, for a flexible processor architecture that can accommodate different types of filter functions in both one and two dimensions.